1. Field of the Invention
The invention relates to an insulated gate field effect transistor and a method of manufacturing the insulated gate field effect transistor.
2. Description of Related Art
An insulated gate field effect transistor described in Japanese Patent Application Publication No. 2007-96034 (JP 2007-96034 A) includes a p-type semiconductor substrate. The semiconductor substrate has an n-type drain region and an n-type source region formed on the surface thereof. A gate electrode is formed on the surface of a channel region which is formed between the drain region and the source region, with a gate insulator interposed between the channel region and the gate electrode.
If an abnormality occurs in the insulated gate field effect transistor due to, for example, supply of an excessively large current or voltage to the transistor, a drain terminal and a source terminal may be short-circuited, that is, a so-called short-circuit fault may occur. If a short-circuit fault occurs in the insulated gate field effect transistor, electric power is constantly supplied to other devices through the transistor. Consequently, the influence on the other devices increases.